As the semiconductor industry advances to the 22 nm technology node, some manufacturers have already begun to consider the problem of how to make transition from a planar CMOS transistor to a three-dimensional (3D) FinFET device structure. Compared to a planar transistor, a FinFET device improves control over the channel, and thus reduces short-channel effect. The gate of a planar transistor is located right over the channel, while the gate of a FinFET device surrounds the channel from two or three sides, thus electrostatic control may be implemented for the channel from two or three sides.
At present, normally there are two types of conventional FinFETs: FinFETs formed on a substrate of a Silicon-On-Insulator (SOI), and FinFETs formed on a substrate of a bulk Si material (Bulk FinFETs). However, using of SOI wafers to make FinFETs is very expensive. In another aspect, it is difficult to make high-quality FinFETs with conventional bulk wafers due to the problems in terms of device width and sub-threshold leakage control.